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PIC18F85J11 FAMILY
DS39774D-page 118
2010 Microchip Technology Inc.
10.2
PIR Registers
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2, PIR3).
Note 1: Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
2: User
software
should
ensure
the
appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.
REGISTER 10-4:
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0
R-0
R/W-0
U-0
R/W-0
PSPIF
ADIF
RC1IF
TX1IF
SSPIF
—TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit
1
= A read or a write operation has taken place (must be cleared in software)
0
= No read or write has occurred
bit 6
ADIF: A/D Converter Interrupt Flag bit
1
= An A/D conversion completed (must be cleared in software)
0
= The A/D conversion is not complete
bit 5
RC1IF: EUSART Receive Interrupt Flag bit
1
= The EUSART receive buffer, RCREG1, is full (cleared when RCREG1 is read)
0
= The EUSART receive buffer is empty
bit 4
TX1IF: EUSART Transmit Interrupt Flag bit
1
= The EUSART transmit buffer, TXREG1, is empty (cleared when TXREG1 is written)
0
= The EUSART transmit buffer is full
bit 3
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1
= The transmission/reception is complete (must be cleared in software)
0
= Waiting to transmit/receive
bit 2
Unimplemented: Read as ‘0’
bit 1
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1
= TMR2 to PR2 match occurred (must be cleared in software)
0
= No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1
= TMR1 register overflowed (must be cleared in software)
0
= TMR1 register did not overflow
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